Field of the Invention
The present invention relates to the field of integrated circuits analysis, and relates more specifically to the methods of analyzing the operation of integrated circuits subjected to thermal stresses.
Description of the Related Art
Before their implementation, integrated circuits are generally subjected to analysis procedures during which these integrated circuits are subjected in particular to stresses representative of operational stresses, i.e. stresses that they are likely to experience in their final environment.
These analysis procedures are particularly important, especially for integrated circuits that have to operate in high-stress environments, such as integrated circuits to be utilized in space and/or military missions, in aircrafts, in power plants, etc.
During an analysis procedure, it is common to subject the integrated circuit in operation to thermal stress, which corresponds for example to an operational thermal stress (thus referred to as an operational test) or thermal stress applied with the aim of accelerating the aging of said circuit (thus referred to as an aging test).
In order to apply thermal stress to an integrated circuit, it is known to place it, together with its test device, in a closed chamber equipped with a heating or cooling system.
“Test device” means the device in which the integrated circuit is mounted to check its operation during the analysis procedure. In particular, the test device comprises at least one printed circuit, called a “motherboard”, on which the integrated circuit is mounted directly or indirectly by means for another printed circuit, called the “daughterboard”, which interfaces with the motherboard.
Other electronic components are mounted on the test device, and it is understood that these components will be subjected to the same thermal stress. If there is a failure, it will be difficult to identify whether the problem comes from the integrated circuit tested, or another electronic component of the test device.
In order to limit the above-mentioned problem, it is known to mount the integrated circuit to be tested on a daughterboard, which is placed in the closed chamber, and to place the motherboard outside the chamber. However, this solution is not applicable for integrated circuits operating at very high frequencies (e.g. gigahertz for current SDRAM DDR3 memories). In effect, when the motherboard and daughterboard are separated, the propagation delay for signals over the interface between the motherboard and the daughterboard becomes far too large, a result of parasite capacities on this interface.
Another problem lies in the fact that the integrated circuits are generally in the form of an electronic chip, at least in part made of a semi-conductive material (silicon, germanium, gallium arsenide, etc.), encapsulated in a housing fitted with external connections (pins, ball grid array, etc.) electrically coupled to the electronic chip.
The thermal stress applied by means for the closed chamber relates to the ambient temperature inside this chamber. This thermal stress is therefore applied to the housing, which is characterized by its own thermal resistance. The temperature of the housing is different from the junction temperature of the electronic chip whereas, in practice, it is this junction temperature that one seeks to control.